1. Field of the Invention
The present invention relates to a semiconductor device that is a master device and a control method thereof, a semiconductor device that is a slave device and a control method thereof, and a data transmission system between a master device and a slave device and a control method thereof. Particularly, the present invention relates to a memory controller that performs high-speed data transfer to and from a memory in synchronization with a clock and a control method thereof, a memory that performs high-speed data transfer to and from a memory controller in synchronization with a clock and a control method thereof, and a data transmission system that performs high-speed data transfer between a memory controller and a memory and a control method thereof.
2. Description of Related Art
In a conventional data transmission system, connection is provided between a controller as a master device, and a semiconductor device as a slave device by a plurality of wirings formed on a board such as a printed circuit board. Although it is desirable that the wirings have an equal length, connection is realized, in practice, by wirings having mutually different lengths, which results in different signal delays in respective wirings.
Therefore, a method of absorbing the difference of signal delay due to wiring has been proposed by providing an input timing circuit in a signal input circuit of a slave device side, and preliminarily adjusting a phase of a clock supplied to the input timing circuit at a master device side (see Japanese Patent Application Laid-open No. H10-228449, for example).
Data transfer speed in data transmission systems has become increasingly faster in recent years. Along with this trend, internal processing speed of devices has been required to be faster accordingly. However, it is becoming a reality that the device characteristic itself cannot catch up with such speeding up.
Accordingly, there is known a method of temporarily receiving, by a plurality of input circuits in a device, system data that are serially transferred to a data terminal at high speed, converting the serial data into parallel data, and processing the parallel data. With this arrangement, the speed of the data processing becomes slower than the transfer speed of data transfer, and thus the internal processing speed can be moderated. Further, a similar effect can also be achieved, when outputting data, by sequentially outputting parallel data that has been processed within the device from a common data terminal using a plurality of output circuits, that is, outputting the parallel data to a system as serial data.
In such a configuration, it is necessary to provide a plurality of input circuits and output circuits connecting in common to a data terminal within the device, therefore it is necessary to supply a plurality of timing signals having different phases respectively to the input circuits and output circuits. The timing signals, generated within the device, are supplied to the input circuits and output circuits via different wirings formed within the device. Although this configuration results in a difference of delay times due to different wiring lengths, it is not as serious as the system level problem mentioned above, that is, the problem of a signal delay difference based on the difference of lengths of connection between a master device and the slave device (signal lines on a system).
However, although it is small as compared with the difference of delay time in the system, the difference of the amount of signal delay based on the difference of wiring lengths of signal lines within the device cannot be avoided. Particularly, because the timing signals (timing signals having different phases) must have phases that match the high-speed data communication, even a slight signal delay can hinder conversions from serial data to parallel data or conversions from parallel data to serial data.
Japanese Patent Application Laid-open No. H10-228449 does not address the problem of phase shifting of timing signals that must be supplied to an input circuit or an output circuits provided in such a common data terminal. Thus, in practice, it is not possible to deal with the problem using the method of Japanese Patent Application Laid-open No. H10-228449.